1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic strain so as to improve the charge carrier mobility.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, substantially depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially influences the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control, since reducing the channel length also requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. According to other approaches, epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, to provide increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates great efforts for the adaptation and possibly the new development of process techniques concerning the above-identified process steps, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length. In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region increases the mobility of electrons, wherein, depending on the magnitude of the tensile strain, an increase in mobility of up to 120% may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Therefore, in some conventional approaches, for instance, a silicon/germanium layer or a silicon/carbon layer is provided in or below the channel region to create tensile or compressive strain therein. Although the transistor performance may be considerably enhanced by the introduction of strain-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding layers into the conventional and well-approved CMOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
In other approaches, stress from an etch stop layer, that is required on top of the transistors to control a contact etch process, is used to induce strain in the channel regions of the transistors, wherein compressive strain is created in the P-channel transistor, while tensile strain is created in the N-channel transistor. However, this conventional approach, although offering substantial performance advantages, may bring about some drawbacks that may partially offset the benefits accomplished by the enhanced strain engineering, as will be described with reference to FIGS. 1a-1d. 
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 150 comprising a first transistor 100N and a second transistor 100P. The transistors 100N, 100P represent different types of transistor elements, such as an N-channel transistor and a P-channel transistor. Although the transistors 100N and 100P differ in their conductivity type, for convenience, the transistors shown have substantially the same configuration and hence corresponding components of the transistors 100N, 100P may be denoted by the same reference numerals, wherein it should be borne in mind that typically any doped regions in one of the transistors 100N, 100P are inversely doped in the other transistor.
The semiconductor device 150 comprises a substrate 101 having formed thereon an insulating layer 102, which may be a buried silicon dioxide layer, a silicon nitride layer and the like, followed by a crystalline semiconductor layer 103 or active layer, which may be a silicon layer. The first and second transistors 100N, 100P may be separated from each other by an isolation structure 120, which may be provided, for instance, in the form of a shallow trench isolation. The first and second transistors 100N, 100P further comprise a gate electrode structure 105 including a semiconductor portion 106, such as a polysilicon portion, and a metal-containing portion 108 that is provided, for instance, in the form of a metal silicide. The gate electrode structure 105 further comprises a gate insulation layer 107 separating the gate electrode structure 105 from a channel region 104, which in turn laterally separates appropriately doped source and drain regions 111 which include corresponding extension regions 114. Moreover, metal silicide regions 112 may be formed in the drain and source regions 111. A spacer element 110 is formed adjacent to the sidewalls of the gate electrode structure 105 and may be separated therefrom by a liner 109. The second transistor 100P may have substantially the same configuration, wherein the channel region 104 and the drain and source regions 111 may include different dopants compared to the respective regions of the transistor 100N.
Moreover, the semiconductor device 150 comprises a first liner or etch stop layer 118 and a second or contact etch stop layer 116 formed above the first etch stop layer 118. The contact etch stop layer 116 is typically formed of silicon nitride having a specific intrinsic stress, whereas the etch stop layer 118 is formed of a different material, such as silicon dioxide, having a high etch selectivity with respect to an etch process for removing a portion of the layer 116, as will be described later on. A thickness of the etch stop layer 118, referred to as 118a, is significantly less compared to a thickness 116a of the contact etch stop layer in order to reduce any deleterious effects of the etch stop layer 118 with respect to the stress transfer efficiency from the contact etch stop layer 116 into the channel region of the transistor 100P when the contact etch stop layer 118 is formed to have a compressive stress. Moreover, the semiconductor device 150 comprises a further etch stop layer 117 formed on the contact etch stop layer 116, which may be comprised of silicon dioxide.
A typical conventional process flow for forming the semiconductor device 150 as shown in FIG. 1a may comprise the following processes. The substrate 101 and the transistors 100N, 100P may be formed according to well-established process techniques, including, for instance, well-established trench isolation techniques for forming the isolation structures 120, followed by a sequence for forming and patterning a gate insulation material and a gate electrode material by means of advanced deposition and/or oxidation, photolithography and etch techniques. Thereafter, implantation sequences and, intermittently, spacer formation techniques may be applied to form the corresponding drain and source regions 111 including the extensions 114 on the basis of one or more spacer elements, such as the spacers 110. Finally, the metal silicide regions 108 and 112 may be formed on the basis of well-established techniques. Thereafter, the first etch stop layer 118 may be formed by depositing silicon dioxide on the basis of, for instance, plasma enhanced chemical vapor deposition (PECVD). Next, the contact etch stop layer 116 may be deposited, for instance, in the form of a silicon nitride layer, wherein the intrinsic stress of the layer 116 may be adjusted by controlling one or more of the deposition parameters, such as the gas mixture, the deposition rate, the temperature and the ion bombardment during the deposition process, in accordance with known techniques. For example, a compressive stress may be obtained up to approximately 1.5 GPa on the basis of well-established process recipes. Thereafter, the etch stop layer 117 is deposited as a silicon dioxide liner.
FIG. 1b schematically shows the device 150 with a resist mask 140 formed thereon, wherein the resist mask 140 covers the transistor 100P while exposing the transistor 100N and the corresponding portions of the layers 118, 116 and 117. Moreover, an etch process 160 is applied in order to remove the exposed portions of the layers 117 and 116. For this purpose, the etch process 160 may comprise a first etch step to etch through the etch stop layer 117 on the basis of a wet chemical process, for instance with diluted fluoric acid, or on the basis of a plasma etch process. Thereafter, the etch process 160 is continued on the basis of an etch chemistry that exhibits a desired high degree of selectivity with respect to the contact etch stop layer 116 and the etch stop layer 118.
FIG. 1c schematically shows the semiconductor device 150 after completion of the etch process 160 and after removal of the resist mask 140. Moreover, any cleaning processes may have been performed to reduce any material residues stemming from the preceding processes. Hence, the device 150 comprises the first etch stop layer 118 above the transistor 100N, so that undue material loss or erosion of the underlying metal silicide regions 108 and 112 during the preceding removal of the layer portion 117 may be effectively suppressed. On the other hand, the second transistor 100P comprises the remaining portion of the contact etch stop layer 116 having the compressive intrinsic stress, thereby inducing a corresponding compressive strain within the channel region 104 in the transistor 100P.
FIG. 1d schematically shows the device 150 in a further advanced manufacturing stage, wherein a second contact etch stop layer 119 is formed above the device that has an intrinsic tensile stress. The second contact etch stop layer 119 is typically comprised of silicon nitride that has been formed by specified process conditions to provide the desired tensile stress therein. Moreover, the semiconductor device 150 has formed thereon a resist mask 170, which covers the first transistor 100N and exposes the second transistor 100P, and thus the respective layers 119, 117, 116 and 118 formed thereabove. In order to reduce undue deleterious effects of the tensile stress of the second contact etch stop layer 119 on the P-channel transistor 100P and to obtain substantially identical conditions during a contact etch in a further advanced manufacturing stage, in which the first and second contact etch stop layers 116 and 119 are used as etch stop layers, the device 150 is subjected to an etch process 180 that is designed to remove the portion of the second contact etch stop layer 119 that is not covered by the resist mask 170. Since well-established selective etch recipes for etching silicon nitride selectively to silicon dioxide are available, the second contact etch stop layer 119 formed above the transistor 100P may be reliably removed without undue damage of the first contact etch stop layer 116 due to the presence of the etch stop layer 117. Thus, the non-removed portion of the layer 119 may provide tensile strain in the transistor 100N, while the first contact etch stop layer 116 may still provide the desired compressive strain in the channel region of the transistor 100P.
However, in highly scaled transistor elements, the stress transfer mechanism has to be highly efficient to result in the desired compressive or tensile strain in the respective channel regions. Consequently, the remaining etch stop layer 118, which is highly advantageous in avoiding undue metal silicide erosion, may, however, significantly reduce stress transfer into the respective channel regions, thereby rendering a conventional technique less efficient.
In view of the above-described situation, there exists a need for an alternative technique that enables the creation of different strain in different transistor elements, while substantially avoiding or reducing effects of at least some of the problems identified above.